The invention relates to a linear regulator and, in particular, to a linear regulator providing a selectable output voltage.
FIG. 1 shows a conventional linear regulator commonly used by those skilled in the art. The bandgap reference circuit provides a stable voltage Vbg. Noise of the voltage Vbg is filtered out by a low pass filter typically comprising an on-chip resistor Rbg and an off-chip capacitor Cbp. The filtered signal Vref is sent to a first input terminal of an error amplifier. In the example shown in FIG. 1, the error amplifier is an operational amplifier and the first input terminal is the negative input of the operational amplifier. A second input, which is the positive input, of the operation amplifier is connected to a first node. A PMOS pass transistor MA is controlled by an output of the error amplifier. As shown in FIG. 1, a drain of the pass transistor MA is treated as the output terminal of the linear regulator. In order to guarantee the output stability of the linear regulator, a large external capacitor COUT is typically connected to the output terminal. A first feedback resistor R1 is connected between the drain of the pass transistor MA and the first node. A second feedback resistor R2 is connected between the first node and the ground. Based on the virtual short between the input terminals of the error amplifier, an output voltage VOUT of the regulator can be adjusted by the ratio of the feedback resistors R1 and R2. As is known in the art, the output voltage VOUT is determined according to the voltage signal Vref, the first and second feedback resistors R1 and R2, and is obtained by
      V    OUT    =            V      ref        ×                  (                  1          +                                    R              1                                      R              2                                      )            .      
For some applications, multiple regulator output voltages are needed. FIG. 2 shows a conventional linear regulator which provides multiple output voltages. As shown in FIG. 2, a bandgap reference circuit is shared by two error amplifiers to reduce the required chip area. The external capacitor Cbp is also typically shared such that the number of pins and external components can be minimized. Two sets of error amplifiers (error amplifiers A and B) and pass transistors (MA and MB) are used and different feedback resistor ratios are provided to generate different output voltages. According to FIG. 2, the output voltages VOUTA and VOUTB can be found to be
      V    OUTA    =            V      ref        ×          (              1        +                              R            A1                                R            A2                              )      and
            V      OUTB        =                  V        ref            ×              (                  1          +                                    R              B1                                      R              B2                                      )              ,respectively.
A linear regulator with a selectable output voltage is disclosed in U.S. Pat. No. 6,593,607 by Nicolas Marty et. al. As shown in FIG. 3, the linear regulator comprises a power MOS transistor 2 controlled by a differential amplifier 5. The differential amplifier 5 has an input terminal 8 receiving, via a circuit of resistors R1, R2, R3 switchable by means of MOS control transistors 12 and 14, a voltage proportional to the output voltage VOUT provided by the regulator. The regulator further includes at least two circuits for generating the control signals CTRL1 and CTRL2 for controlling the respective gates of the control transistors 12 and 14. When the control signals CTRL1 and CTRL2 are respectively at a low and high state, the output voltage VOUT equals
      V    ref    ×            (              1        +                                            R              1                        +                          R              2                                            R            3                              )        .  To the contrary, when the signals CTRL1 and CTRL2 are respectively at a high and low state, the output voltage VOUT equals
      V    ref    ×            (              1        +                              R            1                                              R              2                        +                          R              3                                          )        .  Theoretically, the desired values of the output voltage VOUT can always be achieved by arbitrarily setting the values of the resistors R1, R2, and R3. However, in practical, the values of these resistors cannot be arbitrary ones in consideration of layout matching as well as the output voltage accuracy. This fact makes the choice of the resistors become difficult, especially when the desired levels of the output voltage is more than two, in a design based on the one shown in FIG. 3.